1. Field of the Invention
One embodiment of the present invention disclosed in the specification, drawings, and scope of claims of this application (hereinafter referred to as this specification and the like) relates to a semiconductor device, an operation method thereof, a usage method thereof, a manufacturing method thereof, and the like. Note that one embodiment of the present invention is not limited to these technical fields.
2. Description of the Related Art
A semiconductor device in which a negative potential lower than a ground potential is used is known. For example, in order to reduce subthreshold leakage current, a substrate bias potential in an n-channel MOS transistor is a negative potential, whereas a substrate bias potential in a p-channel MOS transistor is a positive potential (Patent Document 1). In a flash memory, a negative potential is used in accordance with the operation (Patent Document 2).
A negative potential can be generated by a charge pump circuit. Patent Documents 2 and 3 disclose a technique for generating negative potentials with high accuracy. In Patent Documents 2 and 3, a negative voltage output from q charge pump circuit is converted into a positive voltage, the difference between the positive voltage and a positive reference voltage is detected, and the operation of the charge pump circuit is controlled in accordance with the detection results.
A transistor including a metal oxide in a channel formation region (hereinafter, such a transistor may be referred to as an oxide semiconductor transistor or an OS transistor) is known. A variety of semiconductor devices has been fabricated using a CMOS process for a hybrid of an OS transistor and a Si transistor (Non-Patent Documents 1 to 6). As disclosed in Non-Patent Document 6, an OS transistor can be stacked over a Si transistor. In addition, an OS transistor can include a first gate electrode (also referred to as gate or front gate) and a second gate electrode (also referred to as backgate).
Patent Document 4 discloses a memory device using an OS transistor including a first gate electrode and a second gate electrode. For a longer data holding time, a potential lower than a ground potential is input to the second gate electrode. Since the potential of the second gate electrode is a negative potential, the threshold voltage of the OS transistor is shifted on the positive side, and the off-state current of the OS transistor is small.